1. Field of the Invention
The present invention relates to an image sensor and a method of forming the same.
2. Description of the Prior Art
In recent years, complementary metal-oxide semiconductor (CMOS) image sensors have become popular solid image sensors, largely replacing charge-coupled devices (CCD). Because CMOS image sensors are made by conventional semiconductor manufacturing methods, they have both low cost and small size. Otherwise, CMOS image sensors have high quantum efficiency and low read-out noise, and are thus popularly applied in PC and digital cameras.
The typical CMOS image sensor includes a photo diode for metering the intensity of the light, and three or four metal-oxide semiconductors (MOS) individually having the functions of reset, amplification, and selection.
Please refer to FIG. 1. FIG. 1 schematically illustrates a manufacture of an image sensor according to the prior art. An image sensor 100 is installed on a semiconductor substrate 102, wherein the semiconductor substrate is separated into a non-photo receiving area A, and a photo receiving area B. The photo receiving area B has a photo diode 104 in the semiconductor substrate 102. The non-photo receiving area A has a shallow trench isolation (STI) 103 in the semiconductor substrate 102. Two gate electrodes 106, 108 are installed on the semiconductor substrate 102, wherein the gate electrode 108 is installed between the non-photo receiving area A and the photo receiving area B. In prior image sensor 100 manufacture, the shallow trench isolation 103, the photo diode 104, and the gate electrodes 106, 108 are first formed in the semiconductor substrate 102. Then, a covering layer is made by a chemical vapor deposition (CVD) for covering the gate electrodes 106, 108, and the semiconductor substrate 102. An anisotropic etching process is subsequently performed on the covering layer for forming a spacer 110 around the gate electrodes 106, 108. Next, an ion implantation process is performed to form dopants such as the source/drains 116, 118, 120 in the lateral sides of the gate electrodes 106, 108.
A patterned self-alignment silicide block 112 is formed on the photo receiving area B and a part of the gate electrode 108 near the photo receiving area B. A self-alignment silicide (salicide) process is then performed, so salicides 122, 124, 126, 128 are formed on the gate electrode 106, the gate electrode 108 without the self-alignment silicide block 112, and the source/drain respectively.
Subsequently, an anti-reflection layer (AR) 114 is formed on the semiconductor substrate 102. An inter-layer-dielectrics (ILD) layer is then deposited; a photolithograph process of a contact hole is performed, and an etching process of the contact hole is performed, so as to complete other circuits of the CMOS image sensor. In this prior art, the etching process of the spacer 110 usually has ion-bombardment, charge-up damage, and plasma etching damage to the photo-receiving area B, so the noise of the image sensor increases. Otherwise, the anti-reflection layer 114 is installed on the self-alignment silicide block 112, resulting in the material of the self-alignment silicide block 112 not having the function of anti reflection. This means the effect of the anti-reflection layer 114 will not be good enough.
Please refer to FIG. 2. FIG. 2 schematically illustrates a manufacture of an image sensor according to another prior art. An image sensor 200 is installed on a semiconductor substrate 202, wherein the semiconductor substrate is separated into a non-photo receiving area C, and a photo receiving area D. The photo receiving area D has a photo diode 204 in the semiconductor substrate 202. The non-photo receiving area C has a shallow trench isolation 203 in the semiconductor substrate 202. Two gate electrodes 206, 208 are installed on the semiconductor substrate 202, wherein the gate electrode 208 is installed between the non-photo receiving area C and photo receiving area D. In prior manufacture of the image sensor 200, the shallow trench isolation 203, the photo diode 204, and the gate electrodes 206, 208 are first formed in the semiconductor substrate 202. Then, a covering layer (not shown) is made by a chemical vapor deposition (CVD) for covering the gate electrodes 206, 208, and the semiconductor substrate 202. An etching process is then performed on the covering layer for forming a spacer 210 around the gate electrodes 206, 208, a protecting layer 212 on the photo receiving area D and one side of the gate electrode 208 near the photo receiving area D. Next, an ion implantation process is performed to form dopants such as the source/drains 216, 218, 220 in the lateral sides of the gate electrodes 206, 208.
A patterned self-alignment silicide block 214 is then formed on the protecting layer 212 to cover the photo receiving area D and a part of the gate electrode 208 near the photo receiving area D. A self-alignment silicide process is subsequently performed, so salicides 222, 224, 226, 228 are formed on the gate electrode 206, the gate electrode 208 without the self-alignment silicide block 214, and the source/drain respectively. Finally, an anti-refection layer 216 is formed on the semiconductor substrate 202 for the later contact hole process. FIG. 2 discloses the layout of the protecting layer 212 overlapping the gate electrode 208, so as to avoid plasma damage to the photo receiving area D. The stack made by the protecting layer 212, the self-alignment silicide block 214, and the anti-reflection layer 216 is above the photo receiving area D, however. The thickness of the stack is too thick, however, resulting in it influencing the continuous manufacture and product effect.
Because the prior art has the above-mentioned shortcomings, researching an image sensor and method of manufacturing the same that solves the problems of the prior art is an important issue.